While I try to keep my list of publications updated as best as possible here, this is mostly a manual task and may not always be up to date.

For my most updated list of publications, please check my Google Scholar profile or DBLP profile.

Conference Publications

[2020] H. G. M. Hernandez, S. Mahmood, M. Brandalero, M. Hübner. A Modular Software Library for Effective High Level Synthesis of Convolutional Neural Networks. In: ARC 2020, pp. 211-220. [doi]

[2019] M. Brandalero, M. S. 0001, L. Carro, A. C. S. Beck. TransRec: Improving Adaptability in Single-ISA Heterogeneous Systems with Transparent and Reconfigurable Acceleration. In: DATE 2019, pp. 582-585. [doi]

[2019] D. M. Cardoso, R. B. Tonetto, M. Brandalero, L. Agostini, G. L. Nazar, J. R. Azambuja, A. C. S. Beck. Improving Software-based Techniques for Soft Error Mitigation in OoO Superscalar Processors. In: ICECS 2019, pp. 201-204. [doi]

[2019] G. Korol, M. G. Jordan, M. Brandalero, M. B. Rutzig, A. C. S. Beck. Power-Aware Phase Oriented Reconfigurable Architecture. In: ICECS 2019, pp. 626-629. [doi]

[2019] G. Korol, M. G. Jordan, R. S. Silva, M. M. Pereira, M. Brandalero, M. B. Rutzig, A. C. S. Beck. A Runtime Power-Aware Phase Predictor for CGRAs. In: ReConFig 2019, pp. 1-8. [doi]

[2019] A. S. B. Lopes, M. Brandalero, A. C. S. Beck, M. M. Pereira. Generating Optimized Multicore Accelerator Architectures. In: SBESC 2019, pp. 1-8. [doi]

[2019] R. B. Tonetto, D. M. Cardoso, M. Brandalero, L. Agostini, G. L. Nazar, J. R. Azambuja, A. C. S. Beck. A Knapsack Methodology for Hardware-based DMR Protection against Soft Errors in Superscalar Out-of-Order Processors. In: VLSI-SoC 2019, pp. 287-292. [doi]

[2018] P. H. E. Becker, A. L. Sartor, M. Brandalero, T. T. Jost, S. Wong, L. Carro, A. C. S. Beck. A Low-Cost BRAM-Based Function Reuse for Configurable Soft-Core Processors in FPGAs. In: ARC 2018, pp. 499-510. [doi]

[2018] G. F. Oliveira, L. R. Gonçalves, M. Brandalero, A. C. S. Beck, L. Carro. Employing classification-based algorithms for general-purpose approximate computing. In: DAC 2018, pp. 70:1-70:6. [doi][doi]

[2018] M. Brandalero, L. Carro, A. C. S. Beck, M. S. 0001. Approximate on-the-fly coarse-grained reconfigurable acceleration for general-purpose applications. In: DAC 2018, pp. 160:1-160:6. [doi][doi]

[2018] M. Brandalero, G. M. Malfatti, G. F. Oliveira, L. A. d. Silveira, L. R. Gonçalves, B. C. d. Silva, L. Carro, A. C. S. Beck. Efficient Local Memory Support for Approximate Computing. In: SBESC 2018, pp. 122-129. [doi]

[2017] M. Brandalero, A. C. S. Beck. A Mechanism for energy-efficient reuse of decoding and scheduling of x86 instruction streams. In: DATE 2017, pp. 1468-1473. [doi][doi]

[2016] L. A. d. Silveira, M. Brandalero, J. D. d. Souza, A. C. S. Beck. The Potential of Accelerating Image-Processing Applications by Using Approximate Function Reuse. In: SBESC 2016, pp. 122-127. [doi][doi]

[2014] M. Brandalero, A. C. S. Beck. Potential of Using a Reconfigurable System on a Superscalar Core for ILP Improvements. In: SBESC 2014, pp. 43-48. [doi][doi]

[2013] F. M. Capella, M. Brandalero, J. F. Junior, A. C. S. Beck, L. Carro. A Multiple-ISA Reconfigurable Architecture. In: SBESC 2013, pp. 71-76. [doi][doi]

Journal Publications

[2020] M. G. Jordan, M. Brandalero, G. M. Malfatti, G. F. Oliveira, A. F. Lorenzon, B. C. d. S. 0001, L. Carro, M. B. Rutzig, A. C. S. Beck. Data clustering for efficient approximate computing. In: Design Autom. for Emb. Sys., v. 24, p. 3-22, 2020. [doi]

[2020] M. Brandalero, B. N. Lignati, A. C. S. Beck, M. S. 0001, M. Hübner. Proactive Aging Mitigation in CGRAs through Utilization-Aware Allocation. In: CoRR, v. abs/2004.10470, p. None, 2020. [doi]

[2019] M. Brandalero, T. D. Souto, L. Carro, A. C. S. Beck. Predicting performance in multi-core systems with shared reconfigurable accelerators. In: J. Syst. Archit., v. 98, p. 201-213, 2019. [doi]

[2018] P. H. E. Becker, A. L. Sartor, M. Brandalero, A. C. S. Beck. BRAM-based function reuse for multi-core architectures in FPGAs. In: Microprocess. Microsystems, v. 63, p. 237-248, 2018. [doi]

[2018] M. Brandalero, L. A. d. Silveira, J. D. Souza, A. C. S. Beck. Accelerating error-tolerant applications with approximate function reuse. In: Sci. Comput. Program., v. 165, p. 54-67, 2018. [doi]

[2016] M. Brandalero, A. C. S. Beck. Potential analysis of a superscalar core employing a reconfigurable array for improving instruction-level parallelism. In: Design Autom. for Emb. Sys., v. 20, p. 155-169, 2016. [doi]

[2015] F. M. Capella, M. Brandalero, L. Carro, A. C. S. Beck. A multiple-ISA reconfigurable architecture. In: Design Autom. for Emb. Sys., v. 19, p. 329-344, 2015. [doi]